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Verify Boot Process

LOW MODERATE HIGH
1 Overlay 1 Related Control
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Requirements NIST SOURCE

Verify the integrity of the boot process of the following system components: [system components].

Discussion (NIST Supplemental Guidance)

Ensuring the integrity of boot processes is critical to starting system components in known, trustworthy states. Integrity verification mechanisms provide a level of assurance that only trusted code is executed during boot processes.

Implementation Guidance

Engineering Interpretation

Original engineering commentary written for this explorer — not NIST source text and not authoritative guidance.

No engineering interpretation has been authored for SI-7(9) yet. This section is architected to receive it — see the Requirements and Assessment sections above for the authoritative NIST source content in the meantime.

Assessment

NIST SP 800-53A REV 5.2.0

Assessment Objectives

  1. system components requiring integrity verification of the boot process are defined;
  2. the integrity of the boot process of <SI-07(09)_ODP system components> is verified.

Examine

[SELECT FROM: System and information integrity policy; system and information integrity procedures; procedures addressing software, firmware, and information integrity; system design documentation; system configuration settings and associated documentation; integrity verification tools and associated documentation; documentation; records of integrity verification scans; system audit records; system security plan; other relevant documents or records].

Interview

[SELECT FROM: Organizational personnel responsible for software, firmware, and/or information integrity; organizational personnel with information security responsibilities; system developer].

Test

[SELECT FROM: Software, firmware, and information integrity verification tools; mechanisms supporting and/or implementing integrity verification of the boot process].

Overlays

Showing the OT/ICS overlay for the parent control SI-7 — see the SI-7(9) entries within each baseline below.

OT/ICS Overlay SP 800-82r3

NIST SP 800-82r3 Appendix F, Table 22. Blank baseline means the control/control enhancement is not selected in that initial OT baseline.

LOW

Not applicable at this tier.

MODERATE

  • Base control: Included (matches standard baseline)
  • Included: (1) (7)

HIGH

  • Base control: Included (matches standard baseline)
  • Included: (1) (2) (5) (7) (15)

STIGs & CCIs

No STIG checks or CCI mappings are currently loaded for SI-7(9). This section is architected to display, per product: STIG ID, Finding ID, Severity, Title, Description, Check, Fix, CCI, and NIST control mapping — but nothing is populated here until a real DISA STIG/CCI dataset is ingested.

Learn more about STIG/CCI integration →

Evidence

Potential Evidence — Derived

Categorized from the SP 800-53A "Examine"/"Test" artifact list above by keyword — not an authoritative NIST evidence list.

Policy

  • System and information integrity policy
  • system security plan

Configuration

  • system design documentation
  • system configuration settings and associated documentation

Testing

  • Software, firmware, and information integrity verification tools
  • mechanisms supporting and/or implementing integrity verification of the boot process

Other Records

  • system and information integrity procedures
  • procedures addressing software, firmware, and information integrity
  • integrity verification tools and associated documentation
  • documentation
  • records of integrity verification scans
  • system audit records
  • other relevant documents or records